Volume 5 Number 3

This file contains the table of contents of the current papers accepted for publication in ACM Transactions on Design Automation of Electronic Systems. Papers will appear here, as soon as accepted, before the issue goes to print media. After the issue is closed the papers for that issue are filed in the main index.

NOTE: Eager net-hackers, please do NOT put hotlinks to these papers, yet. Things are under construction and will be for a few months yet. We will give out more stable web-referencing information as it becomes available.

ACM Transactions on Design Automation of Electronic Systems

Volume 5 Number 3

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Technical Papers:

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• High Level Library Mapping for Memories
  Pradip Jha & Nikil Dutt
  
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• Efficient Optimal Design Space Characterization Methodologies
  Stephen A. Blythe*, Robert A. Walker
  
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• FILL and FUNI: Algorithms to identify illegal states and sequentially untestable faults
  David Long, * Mahesh Iyer & Miron Abramovici
  
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  Regression-Based Behavioral Power Modeling
  *Alessandro Bogliolo, Luca Benini & Giovanni De Micheli
  
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• Retiming-based Factorization for Sequential Logic Optimization
  Surendra Bommu, Niall O'Neill & Maciej Ciesielski
  
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• CLIP: Integer-Programming-Based Optimal Layout Synthesis of 2-D CMOS Cells
  Avaneendra Gupta*, John P. Hayes
  
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• Stochastic sequental machines systhesis with application to constrained sequence generation
  Diana Marculescu*, Radu Marculescu & Massoud Pedram
  
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• Hardware Software Synthesis of Formal Specifications in Codesign of Embedded Systems
  Vincenza Carchiolo*, Michele Malgeri & Giuseppe Mangioni
  
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• Modeling Layout Tools to Derive Forward Estimates of Area and Delay at the RTL Level
  Donald S. Gelosh & Dorothy E. Setliff*
  
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• Power Optimization of Technology-Dependent Circuits Based on Symbolic Computation of Logic Implications
  R. I. Bahar*, E. T. Lampe & E. Macii
  
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• Timing-Driven Routing for Symmetrical-Array-Based FPGAs
  Yao-Wen Chang, Dr. Kai Kun & Dr. D. F. Wong
  
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• Architectural Level Power Estimation and Design Experiments
  Rita Yu Chen*, Mary Jane Irwin & Raminder S. Bajwa
  
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• On-Chip vs. Off-Chip Memory: The Data Partitioning Problem in Embedded Processor-based Systems
  Preeti Panda*, Nikil D. Dutt & Alexandru Nicolau
  
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• Optimizing Computations for Effective Block-Processing
  Marios C. Papaefthymiou*, Kumar N. Lalgudi and Miodrag Potkonjak
  
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• Synthesis of low-power selectively-clocked systems from high-level specifcation
  Luca Benini & Giovanni De Micheli
  
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• A Codesign Back End Approach for Embedded System Design
  G. Gogniat, M. Auguin*, L. Bianco, and A. Pegatoguet
  
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• Efficient Routability Check Algorithms for Segmented Channel Routing
  Cheng-Hsing Yang, Sao-Jie Chen*, Jan-Ming Ho and Chia-Chun Tsai
  
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• Dynamic State Traversal for Sequential Circuit Test Generation
  Michael S. Hsiao*, Elizabeth M. Rudnick and Janak H. Patel
  
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• Three-Layer Bubble-Sorting-Based Non-Manhattan Channel Routing
  Jin-Tai Yan
  
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• Environment Modeling and Language Universality
  Richard Raimi*, Ramin Hojati, Kedar S. Namjoshi
  
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• Allocation of FIFO Structures in RTL Data Paths
  M. Balakrishnan and Heman Khanna
  
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  Transactions on Design Automation of Electronic Systems, Last changed on 06-Apr-00 01:53 by spl.